Mail Thread Index

• Date Index

• [oc] Delay and latency ?, saumil merchant
  • Re: [oc] Delay and latency ?, Jim Dempsey
  • Re: [oc] Delay and latency ?, John Sheahan
• [oc] New available invented products, dima
• [oc] (No Subject), faradhini yuniar sabara
• [oc] If anyone has a free AMBA AHB to wishbone or AHB master or slave, j1234f
  • <Possible follow-up(s)>
  • Re: [oc] If anyone has a free AMBA AHB to wishbone or AHB master or slave, alan_m_carrspamno
    • Re: [oc] If anyone has a free AMBA AHB to wishbone or AHB master or slave, Richard Herveille
• [oc] Newbie question - matricies and vectors for physics, Sam Hale
  • Re: [oc] Newbie question - matricies and vectors for physics, Lars Segerlund
    • Re: [oc] Newbie question - matricies and vectors for physics, Niclas Hedhman
      • [oc] perlilog, paul
      • Re: [oc] Newbie question - matricies and vectors for physics, Rudolf Usselmann
  • Re: [oc] Newbie question - matricies and vectors for physics, Tom Hawkins
• [oc] K68, Shawn Tan
  • <Possible follow-up(s)>
  • Re: [oc] K68, Shawn Tan
• [oc] Common IP-core metadata standardization, Joachim Strömbergson
• [oc] VHDL Help..., =?ISO-8859-15?B?SOljdG9yIE9y824gTWFydO1uZXo=?=
  • Re: [oc] VHDL Help..., Shehryar Shaheen
    • [oc] wishbone performance, paul
• [oc] Verilog 2001 Synthesis and Accelera, Joachim Strömbergson
• [oc] Verilog 2001 and SystemVerilog, Joachim Strömbergson
• Re: [oc] a question about Verilog coding ..., Sridhar
• [oc] a question about Verilog coding ..., henry_xb
• [oc] 127Hinda Cam,
• [oc] DDR Ram verilog code, kd_apte
• [oc] I want some advice of DMA controller designing, linyis
• Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1, teju-dj
  • Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1, Joachim Strömbergson
• Webpack Install withe wine, was: Re: [oc] linux xilinx webpack programming, Uwe Bonnes
• [oc] writing to files, leire.rubio
  • <Possible follow-up(s)>
  • Re: [oc] writing to files, daniel.mediano
• [oc] wireless mac, cfk
• [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1, Joachim Strömbergson
  • Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1, Damjan Lampret
    • Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1, Niclas Hedhman
    • Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1, Joachim Strömbergson
  • Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1, Tom Hawkins
  • Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1, Rudolf Usselmann
    • Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1, =?UTF-8?B?Sm9hY2hpbSBTdHLDtm1iZXJnc29u?=
      • Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1, Rudolf Usselmann
      • Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1, paul
      • Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1, Rudolf Usselmann
      • Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1, Marco Antonio Simon Dal Poz
      • Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1, Rudolf Usselmann
      • Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1, Marco Antonio Simon Dal Poz
      • Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1, paul
      • Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1, Rudolf Usselmann
      • Verilog vs VHDL (Was: Re: [oc] Verilog coding style...), Joachim Strömbergson
      • Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1, Joachim Strömbergson
      • Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1, Shehryar Shaheen
      • Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1, Joachim Strömbergson
      • Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1, Shehryar Shaheen
      • Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1, Joachim Strömbergson
      • Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1, Shehryar Shaheen
      • Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1, Tom Hawkins
      • Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1, Rudolf Usselmann
      • Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1, Joachim Strömbergson
      • Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1, Anil Sewani
      • Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1, Tom Hawkins
      • Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1, Joachim Strömbergson
      • Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1, Tom Hawkins
      • Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1, Marko Mlinar
      • Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1, Tom Hawkins
      • Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1, Niclas Hedhman
      • Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1, Marko Mlinar
      • Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1, Shehryar Shaheen
      • Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1, Tom Hawkins
      • Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1, Shehryar Shaheen
      • Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1, John Sheahan
      • Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1, Shehryar Shaheen
      • Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1, Rudolf Usselmann
      • Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1, Shehryar Shaheen
      • Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1, Rudolf Usselmann
      • Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1, Tom Hawkins
      • Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1, Niclas Hedhman
      • [oc] Verilog vs VHDL vs Other, Tom Hawkins
      • Re: [oc] Verilog vs VHDL vs Other, Marko Mlinar
      • Re: [oc] Verilog vs VHDL vs Other, Tom Hawkins
      • Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1, Marco Antonio Simon Dal Poz
      • Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1, John Sheahan
      • Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1, Rudolf Usselmann
      • Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1, Marco Antonio Simon Dal Poz
      • Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1, Rudolf Usselmann
      • Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1, H. Peter Anvin
      • Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1, Dian Tresna Nugraha
      • Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1, Joachim Strömbergson
      • Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1, Armando Astarloa
      • Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1, Joachim Strömbergson
      • Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1, Armando Astarloa
      • Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1, Marco Antonio Simon Dal Poz
      • Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1, Nicolas Boulay
      • Language war, was Re: [oc] Verilog coding style ..., Andras Ferencz
      • Re: Language war, was Re: [oc] Verilog coding style ..., Niclas Hedhman
      • [oc] i386 legally, paul
      • Re: [oc] i386 legally, John Dalton
      • Re: [oc] i386 legally, Niclas Hedhman
      • Re: [oc] i386 legally, H. Peter Anvin
      • Re: [oc] i386 legally, Niclas Hedhman
      • Re: [oc] i386 legally, Sudarshan
      • Re: [oc] i386 legally, Joachim Strömbergson
      • Re: [oc] i386 legally, H. Peter Anvin
      • Re: [oc] i386 legally, John Sheahan
      • Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1, Todd Fleming
      • Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1, Rudolf Usselmann
      • OT: Textbook Anecdote (was Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1), John Dalton
      • Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1, Charles Lepple
      • Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1, H. Peter Anvin
      • Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1, Todd Fleming
      • Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1, John Sheahan
      • Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1, John Dalton
      • Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1, Chenbo Liu
      • Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1, Nicolas Boulay
      • Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1, H. Peter Anvin
      • Quartus-II (Was: Re: [oc] Verilog coding style...), =?UTF-8?B?Sm9hY2hpbSBTdHLDtm1iZXJnc29u?=
    • Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1, Bjorn Olsson
      • Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1, Rudolf Usselmann
      • Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1, Niclas Hedhman
      • [oc] lack of howtos, paul
      • Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1, Bjorn Olsson
      • Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1, Rudolf Usselmann
      • Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1, Bjorn Olsson
      • Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1, Rudolf Usselmann
  • <Possible follow-up(s)>
  • Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1, Shehryar Shaheen
• [oc] linux xilinx webpack programming, John Sheahan
  • <Possible follow-up(s)>
  • Re: [oc] linux xilinx webpack programming, lee ainscough
  • Re: [oc] linux xilinx webpack programming, uwe.hartl
    • Re: [oc] linux xilinx webpack programming, John Sheahan
  • Re: [oc] linux xilinx webpack programming, uwe.hartl
    • Re: [oc] linux xilinx webpack programming, Rudolf Usselmann
  • Re: [oc] linux xilinx webpack programming, ben
  • Re: [oc] linux xilinx webpack programming, uwe.hartl
    • Re: [oc] linux xilinx webpack programming, John Sheahan
    • Re: [oc] linux xilinx webpack programming, Tom Hawkins
    • Message not available
      • Message not available
      • Re: [oc] linux xilinx webpack programming, Tom Hawkins
      • Re: [oc] linux xilinx webpack programming, Uwe Bonnes
  • Re: [oc] linux xilinx webpack programming, uwe.hartl
  • Re: [oc] linux xilinx webpack programming, Uwe Bonnes
    • Re: [oc] linux xilinx webpack programming, John Sheahan
  • Re: [oc] linux xilinx webpack programming, uwe.hartl
    • Re: [oc] linux xilinx webpack programming, John Sheahan
      • Re: [oc] linux xilinx webpack programming, Uwe Bonnes
• Re: [oc] AVNET XPA3 CPLD Board, Shehryar Shaheen
• [oc] Dallas 1-Wire Search Algorithm, DirkVanAken
  • Re: [oc] Dallas 1-Wire Search Algorithm, Niclas Hedhman
• [oc] Synthesis with Memory, NansonHuang
• [oc] Altera Cyclone development boards -- SUMMARY, H. Peter Anvin
• [oc] Patents and their applicability, John Dalton
  • Re: [oc] Patents and their applicability, Rudolf Usselmann
  • Re: [oc] Patents and their applicability, Marko Mlinar
  • Re: [oc] Patents and their applicability, Niclas Hedhman
• [oc] =?GB2312?B?w+K30b+0yKvH8rXnytOjocnMxvO1xND7tKvK19Gho6E=?= 8:2:, =?GB2312?B?sbG+qczGt+fOxLuvvbvB99bQ0MQ=?=
• RE: [oc] i want code of uart16550, gvvss
• [oc] licensing made easy (2nd try), Rudolf Usselmann
  • Re: [oc] licensing made easy (2nd try), John Dalton
    • Re: [oc] licensing made easy (2nd try), Niclas Hedhman
• Re: [oc] MP3 decoder?, gzy_2003
• [oc] Newbie, first proto board, Cyrus and Kristi
  • Re: [oc] Newbie, first proto board, Shehryar Shaheen
  • <Possible follow-up(s)>
  • Re: [oc] Newbie, first proto board, xerxes
  • Re: [oc] Newbie, first proto board, xerxes
• [oc] Altera development boards?, H. Peter Anvin
• [oc] Video Timing generator(RS170) interlaced in VHDL help, edwinstuff
  • Re: [oc] Video Timing generator(RS170) interlaced in VHDL help, John Kent
• [oc] urgency, =?gb2312?B?wfUg0MQ=?=
  • <Possible follow-up(s)>
  • RE: [oc] urgency, sphuynh
• [oc] Automatic Core Metrics and Documentation, Tom Hawkins
  • Re: [oc] Automatic Core Metrics and Documentation, John Dalton
    • Re: [oc] Automatic Core Metrics and Documentation, Charles Lepple
  • Re: [oc] Automatic Core Metrics and Documentation, Niclas Hedhman
    • Re: [oc] Automatic Core Metrics and Documentation, Rudolf Usselmann
      • Re: [oc] Automatic Core Metrics and Documentation, Niclas Hedhman
    • Re: [oc] Automatic Core Metrics and Documentation, Tom Hawkins
      • Re: [oc] Automatic Core Metrics and Documentation, Graham Seaman
      • Re: [oc] Automatic Core Metrics and Documentation, Rudolf Usselmann
      • Re: [oc] Automatic Core Metrics and Documentation, Graham Seaman
      • Re: [oc] Automatic Core Metrics and Documentation, Rudolf Usselmann
      • Re: [oc] Automatic Core Metrics and Documentation, John Dalton
      • Re: [oc] Automatic Core Metrics and Documentation, John Dalton
      • Re: [oc] Automatic Core Metrics and Documentation, Graham Seaman
      • Re: [oc] Automatic Core Metrics and Documentation, Niclas Hedhman
      • Re: [oc] Automatic Core Metrics and Documentation, Miha Lampret
      • Re: [oc] Automatic Core Metrics and Documentation, Tom Hawkins
      • Re: [oc] Automatic Core Metrics and Documentation, Jim Dempsey
      • Re: [oc] Automatic Core Metrics and Documentation, Tom Hawkins
      • Re: [oc] Automatic Core Metrics and Documentation, Charles Lepple
      • file generation (was :Re: [oc] Automatic Core Metrics and Documentation), Nicolas Boulay
      • Re: [oc] Automatic Core Metrics and Documentation, Niclas Hedhman
      • [oc] AVNET XPA3 CPLD Board, Umair Farooq Siddiqi
      • Re: [oc] AVNET XPA3 CPLD Board, Shehryar Shaheen
• Re: [oc] Inquiry (Replied off List), nico
• [oc] QPSK / 8-PSK / QAM Modem., nissimd
  • Re: [oc] QPSK / 8-PSK / QAM Modem., Haytham
  • <Possible follow-up(s)>
  • Re: Re: [oc] QPSK / 8-PSK / QAM Modem., henry_xb
• Re: [oc] T80 cpu version 0242 released, hpa
  • Re: [oc] T80 cpu version 0242 released, MikeJ
    • Re: [oc] T80 cpu version 0242 released, H. Peter Anvin
      • Re: [oc] T80 cpu version 0242 released, Richard Herveille
      • Re: [oc] T80 cpu version 0242 released, H. Peter Anvin
• [oc] vhdl2verilog, sudarshan
• Re: [oc] QAM DEMODULATOR, filippo.tigli
• [oc] square circuts, haoguang.guo
  • Re: [oc] square circuts, John Sheahan
  • <Possible follow-up(s)>
  • re: [oc] square circuts, lin.sheng
  • Re: [oc] square circuts, haoguang.guo
• [oc] RAM memory, leire.rubio
  • Re: [oc] RAM memory, Joachim Strömbergson
• Re: Re: [oc] ARM Core, nissimd
• [oc] how to express the phase in digital circut?, henry_xb
• [oc] Inquiry, Rudolf Usselmann
  • Re: [oc] Inquiry, John Dalton
    • Re: [oc] Inquiry, Rudolf Usselmann
      • Re: [oc] Inquiry, Stuart Brorson
      • Re: [oc] Inquiry, John Dalton
      • Re: [oc] Inquiry, Rudolf Usselmann
      • Re: [oc] Inquiry, Stuart Brorson
      • Re: [oc] Inquiry, John Dalton
      • Re: [oc] Inquiry, niclas
      • Re: [oc] Inquiry, Rudolf Usselmann
      • Re: [oc] Inquiry, John Sheahan
      • Re: [oc] Inquiry, John Dalton
      • Re: [oc] Inquiry, Colin Marquardt
      • Re: [oc] Inquiry, Niclas Hedhman
      • Re: [oc] Inquiry, Marko Mlinar
  • <Possible follow-up(s)>
  • Re: [oc] Inquiry, nicO
  • Re: [oc] Inquiry, John Dalton
    • Re: [oc] Inquiry, Stuart Brorson
      • Re: [oc] Inquiry, Marko Mlinar
      • Re: [oc] Inquiry, Richard Herveille
      • Re: [oc] Inquiry, Damjan Lampret
      • Re: [oc] Inquiry, Richard Herveille
      • Re: [oc] Inquiry, Richard Herveille
      • [oc] Sonics Inc misleadin posting, Rudolf Usselmann
      • Re: [oc] Inquiry, Richard Herveille
      • Re: [oc] Inquiry, Rudolf Usselmann
      • Re: [oc] Inquiry, Rudolf Usselmann
      • Re: [oc] Inquiry, Stuart Brorson
      • Re: [oc] Inquiry, Richard Herveille
      • Re: [oc] Inquiry, Stuart Brorson
      • Re: [oc] Inquiry, John Dalton
      • Re: [oc] Inquiry, Niclas Hedhman
      • [oc] licensing made easy, Rudolf Usselmann
      • Re: [oc] Inquiry, John Sheahan
  • Re: [oc] Inquiry, cyrano
  • Re: [oc] Inquiry, Billditt
    • Re: [oc] Inquiry, Rudolf Usselmann
      • Re: [oc] Inquiry, Marko Mlinar
      • Re: [oc] Inquiry, Rudolf Usselmann
      • [oc] Voting [WAS: Re: Inquiry], Marko Mlinar
      • Re: [oc] Inquiry, Colin Marquardt
      • Re: [oc] Inquiry, Niclas Hedhman
      • Re: [oc] Inquiry, Rudolf Usselmann
      • Re: [oc] Inquiry, Niclas Hedhman
      • Re: [oc] Inquiry, Rudolf Usselmann
      • Re: [oc] Inquiry, John Dalton
      • [oc] Re: Inquiry, Andreas Bombe
      • Re: [oc] Inquiry, Charles Lepple
      • Re: [oc] Inquiry, Rudolf Usselmann
      • Re: [oc] Inquiry, Niclas Hedhman
      • Re: [oc] Inquiry, Rudolf Usselmann
      • [oc] Re: Inquiry, Andreas Bombe
  • Re: [oc] Inquiry, nico
    • Re: [oc] Inquiry, Niclas Hedhman
      • Re: [oc] Inquiry, Johan Klockars
      • Re: [oc] Inquiry, Joachim Strömbergson
      • Re: [oc] Inquiry, Niclas Hedhman
      • Re: [oc] Inquiry, John Dalton
      • Re: [oc] Inquiry, Niclas Hedhman
      • Re: [oc] Inquiry, John Kent
      • Re: [oc] Inquiry, Rudolf Usselmann
      • Re: [oc] Inquiry, John Kent
      • Re: [oc] Inquiry, Rudolf Usselmann
      • Re: [oc] Inquiry, Marko Mlinar
      • Re: [oc] Inquiry, Niclas Hedhman
      • Re: [oc] Inquiry (Replied off List), John Dalton
      • OT: Re: [oc] Inquiry, John Dalton
      • [oc] USB and VME bus, pom gud
      • [oc] Re: USB and VME bus, Andreas Bombe
      • Re: [oc] USB and VME bus, Charles Lepple
  • Re: [oc] Inquiry, cyrano
  • Re: [oc] Inquiry, cyrano
    • Re: [oc] Inquiry, Rudolf Usselmann
      • Re: [oc] Inquiry, Niclas Hedhman
      • Re: [oc] Inquiry, Rudolf Usselmann
    • Re: [oc] Inquiry, Niclas Hedhman
      • Re: [oc] Inquiry, Nicolas Boulay
      • Re: [oc] Inquiry, H. Peter Anvin
      • Re: [oc] Inquiry, Niclas Hedhman
  • Re: [oc] Inquiry, cyrano
  • Re: [oc] Inquiry, cyrano
• [oc] VHDL Designers are needed, konstantinos_aris
• [oc] PID controller in FPGA?, jwen
  • Re: [oc] PID controller in FPGA?, Charles Lepple
    • Re: [oc] PID controller in FPGA?, niclas
  • RE: [oc] PID controller in FPGA?, Renaux Jacky