Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1

["H. Peter Anvin" <hpa@zytor.com>]

Rudolf Usselmann wrote:
> 
> Most people who are using FPGAs, don't want to spend the $2K (?) for
> the full version of the Xilinx tools that are commercially available.
> They prefer to use the Web-pack ! Makes me laugh each time I see them
> complaining how shitty the web-pack is ! You see these two markets
> have been always separated by a big cost difference. FPGA guys want
> everything free, ASIC guys are used to spend 6 digit sums on tools.
> 

If your volume are in the single or double digits, paying $2K for tools
may very well be unreasonable.  You don't do ASICs unless volumes are
way high.

	-hpa (I work for a CPU vendor... I see the whole spectrum...)



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