Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1

[Marco Antonio Simon Dal Poz <mdalpoz@lsi.usp.br>]

On 21 May 2003, Rudolf Usselmann wrote:

> > > If you don't trust me, please check John Cooleys trip reports for the latest 
> > > DAC and SNUG [1]. Yes, SNUG is a Synopsys event, but you can probably trust 
> > > your fellow engineers when it comes to the tool polls.
> > 
> > Thanks for the URLs. But Synopsys leadership is not too far away from
> > Cadence.
> 
> Synopsys was one of the first companies to write a decent
> synthesis tool. Before there was design compiler, all we
> had where the Berkley tools. And I can tell you, it was a
> pain in the neck.
> When Synopsys released the first DC, it was like a new
> millennium in chip design has begone. And it did.

Thanks for the info. As a matter of fact, when I started in ASIC design,
DC was already available, so I never tried previous tools.
Anyway, Synopsys is dominant for historical reasons, but nowadays is it
still the best tool for ASIC design?

> The only reason Synopsys tried to get in to the FPGA market
> was because there was only the usual crap available from the
> FPGA vendors. Synopsys customers (many use FPGAs for prototyping),
> have asked them to support FPGAs. Synopsys is/has never been
> interested in this market, but was mostly doing it a a favor
> to it's customers. When Synplify and Leonrdo came along, they
> where doing a much better job on FPGAs because that was thei
> main business.

I think that FPGA Express had done a great job, but didn't evolve as
others specific FPGA tools did. As there is a trend of junction of several
tools in one big packet (e.g. Cadence has tools of IC layout, HDL
sinthesis and even PCB schematic and layout!) for entire system design,
there should be interest from Synopsys in FPGA, just for tool
completion. For the user, it is interesting that only one tool could do
all the job (including FPGA prototyping) because it is common that FPGA
specific tools (from FPGA vendors) just support a subset of the HDL used
(as Xilinx and Altera always did).

> > I am used to do FPGA hardware design with Verilog and VHDL, and I can't
> > see why Verilog is so better than VHDL. In fact, I see advantages and
> > disadvantages in both sides, so, why Verilog is still dominant?
> 
> I guess everybody forgot to ask you !

I think you misunderstood me. I didn't say VHDL is better, I just would
like to know why Verilog was choosen. As you also prefer Verilog, I would
like to listen to your opinion.

> Just send an email to Sun, CISCO, 3com, Motorola, TI, etc., etc.
> and tell them how stupid they all are for using Verilog and how
> VHDL is much better !

Please, read again my paragraph. I never said one or better than the
other. But if each one has strong and weak points, why the market share of
each other is not 50%?

Best Wishes,
Marco Antonio

--
To unsubscribe from cores mailing list please visit http://www.opencores.org/mailinglists.shtml