[oc] Synthesis with Memory

[NansonHuang@ITRI.ORG.TW]

 Hi, dear opencores elites,

   I have a design with embedded SSRAM. The SSRAM is generated with artisan
memory compiler as hard macro. The DUT include the sram. The problem comes
up with if I set dont touch on the sram and synthesis the whole DUT+sram
together. Or just left the DUT
to synthesis and describe the interface timing with ssram. Both DUT and
sram feed the same clock. Which is better to DC and get better results ?

 Appreciate for your any comments.

 Nanson


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