Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1

[Tom Hawkins <tom1@launchbird.com>]

On Friday 16 May 2003 11:24 am, Joachim Strömbergson wrote:
> Aloha!
>
> One specific thing in Verilog is the (mis)use of the delay operator
> "#". There are several cores with RTL code that contains this
> operator. Trust me, this is very wrong. Case in point, the SHA1
> core by Paul Hartke. In the top level entity, you can see:
>
> All synthesis tools will produce warning about "#" not being a
> synthesisable operator. Some, Altera Quartus-II will choke. None of
> them will generate hardware that have been generated due to the "#"
> operator.
>
> Let me restate this so it's totally clear: If you use "#" in the
> RTL to get a specific behaviour during simulation, then you can be
> dead certain that the real life behaviour of the generated HW will
> have a different behaviour.
>
> "#" belongs in the testbench and specific simulations models only.
> Period.

I'll go a step further by saying '#' doesn't even belong in the test 
bench.  I remember testing my first Verilog module by stimming inputs 
coded with '#' for each clock cycle.  The resulting waveforms made it 
appear as if registers were not updating values correctly.  It wasn't 
until later I realized my simulator was trying to schedule two 
ambiguous events: clock and data changing state at the same time.

Since then, I code everything within the synthesizable subset -- 
design modules and verification components alike.  '#' only shows up 
in one spot:

forever  begin
  #1 clock = 1; clock = 0;
end;

-Tom


-- 
Tom Hawkins
Launchbird Design Systems, Inc.
952-200-3790
tom1@launchbird.com
http://www.launchbird.com/


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