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Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1
Aloha!
Damjan Lampret wrote:
> Heya !
>
> There is a document that tries to address exactly this issue. It is called
> OpenCores Coding Guidelines. It might not have all the information (it is a
> working document so all contributions that make sense are welcome) but I
> think it is a good starting point. PDF is available here:
> http://www.opencores.org/cgi-bin/cvsget.cgi/common/opencores_coding_guidelin
> es.pdf
>
> Source:
> http://www.opencores.org/cgi-bin/cvsget.cgi/common/opencores_coding_guidelin
> es.doc
>
> Also see FAQ
>
> #4.3 Does OpenCores have any coding and interface guidelines?
>
> The OpenCores coding guidelines are available at
> http://www.opencores.org/cgi-bin/cvsget.cgi/common/opencores_coding_guidelin
> es.pdf. Also have a look at some of the compliant cores, such as the
> 'wishbone' and 'common' cores.
Ok, now I know why I wear glasses. ;-)
Thanks. I'll review the documents and send comments.
The one I found was the "Coding Conventions" on the OpenIPCore page, which is
VHDL only.
One silly question: How does OpenIPCore relate to OpenCores? Since there
obviously are Design Guidelines for VHDL in OpenIPCore and also in the normal
OpenCores, one (i.e. me) could get the impression that they are somehow two
slightly different things. Yet, when they share the webpage thet are related?
This time I did look in the FAQ.
--
Med vänlig hälsning, Yours
Joachim Strömbergson - Alltid i harmonisk svängning.
VP, Research & Development
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