Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1

[Rudolf Usselmann <rudi@asics.ws>]

On Wed, 2003-05-21 at 15:18, paul wrote:
...
> >  
> >
> Allow a student to inject some comments. I was taugh PASCAL in grade 11, 
> and Modula-2 in freshman year, but the world is using C.
> I really don't want to end up learning "PASCAL" or "modula-2" (VHDL) 
> while I must use C (verilog) in work....
> Or the converse....

Paul,

when I was a student/fresh graduate I thought the same
way !
But now I think it was good to have learned some other
languages. It gives you a better perspective on what is
out there and lets you appreciate a better choice instead
of always wondering weather PASCAL wouldn't have been a
better choice !

Also as a side not: I heard many people say that is is
easier to go from VHDL to Verilog than from verilog VHDL.

Cheers !
rudi               
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