Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1

[Marco Antonio Simon Dal Poz <mdalpoz@lsi.usp.br>]

On 20 May 2003, Rudolf Usselmann wrote:

> > > You should ask your school (and the other schools you are
> > > referring too), most of the industry is using Verilog.
> > > Search the archives, I have posted a message a while back
> > > in which the Synopsys CEO makes a statement that VHDL is
> > > dead. Which is probably not quite true, but shows you that
> > > the industry is at least trying to steer in to one direction ...
> > 
> > AFAIK, the industry is trying to steer in the direction of discarding
> > Synopsys. Please, correct me if I am wrong...
> 
> You are wrong, very wrong.
> Synopsys is one of the Industry leaders.

Maybe I forgot to specify that I was talking about the FPGA world.
Anyway, why do FPGA vendors tools are discarding the use of Synopsys FPGA
Compiler? Recently I compared performance obtained with FPGA Compiler and
Cadence tools. I noticed a better synthesis time and higher clock
frequencies achievable using Cadence.

Marco Antonio

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