Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1

[Rudolf Usselmann <rudi@asics.ws>]

On Tue, 2003-05-20 at 20:28, Marco Antonio Simon Dal Poz wrote:
> On 20 May 2003, Rudolf Usselmann wrote:
> 
> > > I'm new here. I see most of the projects are done in Verilog. Why Verilog?
> > > Most school teach VHDL.... My university teach VHDL.
> > > I really don't want to juggle two languages.
> > 
> > You should ask your school (and the other schools you are
> > referring too), most of the industry is using Verilog.
> > Search the archives, I have posted a message a while back
> > in which the Synopsys CEO makes a statement that VHDL is
> > dead. Which is probably not quite true, but shows you that
> > the industry is at least trying to steer in to one direction ...
> 
> AFAIK, the industry is trying to steer in the direction of discarding
> Synopsys. Please, correct me if I am wrong...

You are wrong, very wrong.

Synopsys is one of the Industry leaders.


> Best Wishes,
> 
> Marco Antonio


rudi               
-------------------------------------------------------
www.asics.ws  -- Solutions for your ASIC/FPGA needs ---
---------------- FPGAs * Full Custom ICs * IP Cores ---
* * * FREE IP Cores  --> http://www.asics.ws/ <-- * * *

--
To unsubscribe from cores mailing list please visit http://www.opencores.org/mailinglists.shtml