Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1

[Shehryar Shaheen <shehryar.shaheen@ul.ie>]

----- Original Message -----
From: "John Sheahan" <jrsheahan@optushome.com.au>
To: <cores@opencores.org>
Sent: Thursday, May 29, 2003 11:38 PM
Subject: Re: [oc] Verilog coding style for Open Cores-RTL - Case in point
SHA1


> On Thu, May 29, 2003 at 10:26:48PM +0100, Shehryar Shaheen wrote:
> >
> > > Is there any quickly way to code a netlist given a
> > > handful of components without having to worry about execution order?
> >
> > All declared concurent processes will execute in parallel much like all
> > always blocks
> >  in verilog execute in parallel and all processes in VHDL.
>
> you appear to have ducked this question. Instantiations and assigns
> are parallel too, and are short and clear.

Modules can be instatiated in SystemC.
Like the yxz module can be instatited like

xyz  xyz_inst("xyz_1");
  xyx_inst.clock( -- signal to connect to--);
  xyz_inst.din1  (-- signal to connect to --);
  xyz_inst.din2  (-- signal to connect to --);
  xyz_inst.dout1(-- signal to connect to --);
  xyz_inst.dout2(-- signal to connect to --);

For SystemC equivalent of assign

first a simple verilog module with an assign

module abc(
 din1
,din2
,sel
,dout1);

input din1;
input din2;
output dout1;

assign  dout1 = sel ? din1 : din2;
endmodule

In SystemC

SC_MODULE(xyz)
{
sc_in<bool> din1;
sc_in<bool> din2;
sc_out<bool> dout1;
void func()
{
dout1 = sel ? din1 : din2;
};
SC_CTOR(xyz)
{
SC_METHOD(func);
sensitive << din1 << din2;
}
};






> john
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