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Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1

To: cores@opencores.org
Subject: Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1
From: John Dalton <john.dalton@bigfoot.com>
Date: Tue, 20 May 2003 11:20:36 +1000
In-Reply-To: <1053365725.1352.55.camel@linux8k>; from rudi@asics.ws on Tue, May 20, 2003 at 03:35:26 +1000
References: <3EC510C6.2090801@InformAsic.com> <1053161255.3456.154.camel@linux8k> <3EC88238.6070403@InformAsic.com> <1053365725.1352.55.camel@linux8k>
Reply-To: cores@opencores.org
Sender: owner-cores@opencores.org

> ... There is no
> QA, or even such basic things as verification at OC. Designers
> verify their own cores ! This is horrible in my opinion. ...

The theory of opensource/free is that, in addition to any
verification by authors, users will verify each core and
contribute bug fixes.

To me this indicates that two actions should increase the
quality of OpenCores:

1) Add a bug tracking system to OpenCores.
2) Instill a culture among uses that fixes and bug reports
   should be contributed back to OpenCores (via the bug
   tracking system).

Regards
John
--
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Follow-Ups:
- Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1
  - From: Nicolas Boulay <nico@seul.org>
- Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1
  - From: "Chenbo Liu" <philewar@icc.sh.cn>

References:
- [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1
  - From: Joachim Strömbergson<Joachim.Strombergson@InformAsic.com>
- Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1
  - From: Rudolf Usselmann <rudi@asics.ws>
- Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1
  - From: =?UTF-8?B?Sm9hY2hpbSBTdHLDtm1iZXJnc29u?=<Joachim.Strombergson@InformAsic.com>
- Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1
  - From: Rudolf Usselmann <rudi@asics.ws>

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