Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1

[Rudolf Usselmann <rudi@asics.ws>]

On Wed, 2003-05-28 at 20:04, Tom Hawkins wrote:
> On Tuesday 27 May 2003 10:29 pm, Rudolf Usselmann wrote:
> > On Wed, 2003-05-28 at 02:20, Tom Hawkins wrote:
> > > On Tuesday 27 May 2003 11:58 am, Shehryar Shaheen wrote:
> > > > So what would Sytem Verilog have in the offing that
> > > >  SystemC doesn't ?
...
> > >
> > > SystemC is not popular because C, object-orientation, and
> > > imperative programming are very poor languages and paradigms for
> > > describing hardware systems.
> >
> > I have to disagree here, Tom. It's not the Object Oriented aspect
> > that make a language like SystemC dis-liked by most HW designers.
> > Matter of fact, Object Oriented languages are quite popular, look
> > at Vera and E.
> 
> Rudi, I agree with you here.  OO works well in the test bench.  But 
> for synthesizable RTL, how often you you code a StateMachine class 
> that inherits from BaseStateMachine and extend the Reset and 
> StateTransistion methods?

Actually I think OO could work very well for synthesizable code
as well. Interfaces definitions come to mind, that could be
extended and overloaded etc. I could also envision writing IP
cores that are later extended using OO techniques. I might
offer different flavors of an IP core that I sell at different
costs/configuration. Vera was not synthesizable, but I really
liked some of it's OO constructs and believe they could be made
synthesizable.

> SystemVerilog will also support the new tax laws.  This will really 
> help me out with my 1040s and 1099s next April. ;-)

:*) To bad for the rest of us who are outside of the US. We will
use the 1040s as scratch paper I guess !

(For the non US people 1040 and 1099 are standard US tax reporting
forms which are hated by everybody equally :*)

> The only thing lost by all this new stuff is implementation.  A lot of 
> tools don't even completely support Verilog-2001 yet.  Synopsys will 
> be the only company with broad SystemVerilog support for the distant 
> future.  Remember, they bought Co-Design, the creators and 
> implementors of SuperLog.  It only makes sense for Synopsys to push 
> for SystemVerilog; most of the work has already been done for them.

I don't know. If Art thinks about it, I think he will realize
that the only way he can push SystemVerilog is by making it a
Standard, an open standard preferably. Otherwise it will die
a pain full death like Vera did ...

> -Tom

Regards,
rudi               
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