Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1

[Rudolf Usselmann <rudi@asics.ws>]

On Wed, 2003-05-21 at 14:50, Bjorn Olsson wrote:
> >>
> >>Such as: module Kalle(PARAMETER_1, PARAMETER_2, etc...)
> > 
> > 
> > This is not how parameters are being passed. This how
> > you pass signals/wires/connections.
> 
> I know the difference. I just would not pass a parameter the way you
> use it. But again, if OC guide lines forced me to write it like that,
> I would probably do it, for conformity reasons... ;-)

You are missing my point, there is NO OTHER way to pass
parameters. 


> >>Ha de!
> > 
> > 
> > I hope this means something nice ! ;*)
> 
> It actually does. Short for "have a nice day" sort of...

Ahh, well, then "Ha de" to you too ! :*)

> Ha de!
> 
> /Bjorn

Cheers, 
rudi               
-------------------------------------------------------
www.asics.ws  -- Solutions for your ASIC/FPGA needs ---
---------------- FPGAs * Full Custom ICs * IP Cores ---
* * * FREE IP Cores  --> http://www.asics.ws/ <-- * * *

--
To unsubscribe from cores mailing list please visit http://www.opencores.org/mailinglists.shtml