Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1

[Shehryar Shaheen <shehryar.shaheen@ul.ie>]

So what would Sytem Verilog have in the offing that
 SystemC doesn't ?

Would you think that the reason that SystemC is not popular is
 cause the learning curve associated with a new language tends
 to put off many users who already have a firm grip over current
 HDLs ?


----- Original Message -----
From: "Joachim Strömbergson" <Joachim.Strombergson@InformAsic.com>
To: <cores@opencores.org>
Sent: Tuesday, May 27, 2003 3:51 PM
Subject: Re: [oc] Verilog coding style for Open Cores-RTL - Case in point
SHA1


Aloha!

Shehryar Shaheen wrote:
> SystemC is more for system modeling (HW+SW) some
>  complex SoCs like the E-GOLD GSM Chipset from Infenieon
>  used SystemC in it's design process.
>
> Siemens has also been using SystemC for ATM chipsets.

ATM - Which is also a dead technology BTW. ,-)

(Sorry couldn't resist)

> Sysnopys already has the CoCentric compiler for SysyemC synthesis
>  and also at the DAC 2003 Synopsys would be showing up at the
>  SystemC booth.
>
> If you look at the RTL subset of SystemC you'll notice that it's very
> similar
>  to VHDL or Verilog RTL subset. So in terms of syhthesis people who don't
> have
>  experience with pure HDLs won't be able to just write some code in C++
and
>  turn it into hardware.
>
> But we'll probably see more executable specifications for SoCs being
written
>  in SystemC.

Trust me, I have used basically basically all tools available on the market
for SoC-modelling (they generally suck pretty badly) and been involved in
writing a few proprietary models and tools myself.

I'm also aware that there are places where SystemC is used. What I refer to
is
that among peers (according to stats from DAC, comments in ESNUG etc),
SystemC
is not popular. And even more importantly among peers, SystemC doesn't seem
to
solve problems in a way more productive way that people are doing today.

What have also become quite clear is that many sites that have been using or
are using SystemC are doing so because high-level management have decided on
using SystemC, not because the engineering department have asked for it.

I have also been on presentations by EDA vendors where the argument *for*
SystemC have been that by using SystemC, "cheap SW designers" (as in low
salaries) can build ASICs. That have been the argument and some managers are
buying in to that.

It's a similar to the argument used by some to promote graphical design
entry
tools, where knowledge about hardware somehow is not needed when you can
draw
FSMs, flowcharts etc.

--
Med vänlig hälsning, Yours

Joachim Strömbergson - Alltid i harmonisk svängning.
VP, Research & Development
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