Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1

[Marco Antonio Simon Dal Poz <mdalpoz@lsi.usp.br>]

On Tue, 20 May 2003, [ISO-8859-1] Joachim Strömbergson wrote:

> > AFAIK, the industry is trying to steer in the direction of discarding
> > Synopsys. Please, correct me if I am wrong...
> 
> <rant>
> You are wrong. ;-)

Ok, I forgot to tell I was talking about FPGAs. I hadn't imagine that ASIC
market was that different from FPGA market.

> There are specific areas where Cadence, Mentor et al are big and
> dominate, but for large parts of the ASIC design flow, Synopsys not
> only dominate but have gained market share. This has both to do with
> the (so far) successful merger with Avanti, but old Synopsys tools
> have in same cases increased market share (where it is possible - for
> STA PrimeTime is basically alone anyways).

What is the big deal with Synopsys tools that it has been chosen as THE
tools and not Cadence and MG tools?

> If you don't trust me, please check John Cooleys trip reports for the latest 
> DAC and SNUG [1]. Yes, SNUG is a Synopsys event, but you can probably trust 
> your fellow engineers when it comes to the tool polls.

Thanks for the URLs. But Synopsys leadership is not too far away from
Cadence.

> One area *not* dominated by Synopsys is FPGAs. But it's a pretty slim market 
> in terms of money, and the free tool offerings from Xilinx and Altera are 
> eating away the margins from below.

I don't think the problem is the margins, I think it's the performance and
the results provided by Synopsys tools against tools provided by Cadence
and MG, because, in the end, tools provided by FPGA manufacturers are
directly based on commercial tools (Synopsys, Cadence or MG). Since Xilinx
cancelled its agreement with Synopsys, I noticed a great improvement in
performance and computational cost of the new Xilinx tools. What is the
reason for that?

> And when it comes to VHDL vs Verilog vs Superlog/System Verilog and SystemC, 
> if engineer like/disklike is a measure, Verilog will *continue* to dominate 
> for the next years and slowly be replaced by System Verilog. And, yes, forget 
> VHDL and SystemC.
> </rant>

I am used to do FPGA hardware design with Verilog and VHDL, and I can't
see why Verilog is so better than VHDL. In fact, I see advantages and
disadvantages in both sides, so, why Verilog is still dominant?

Best wishes,

Marco Antonio


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