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Re: [oc] a question about Verilog coding ...

As far as I know, it cannot. where as in VHDL operator overloading is possible. we can say this is one limitation in verilog. 

Regards,
Sridhar
Team leader
Wireless Design group
nandulasridhar@yahoo.com

cores@opencores.org wrote:
Hi friend£¡

   whether the verilog can overload a operater ? if can ,how?
			
Best Regard
 
				 
¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡henry_xb
¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡xxiaobin@263.net
¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡2003-05-22






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