Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1

["Todd Fleming" <todd@flemingcnc.com>]

> On Tue, 2003-05-20 at 17:42, paul wrote:
> > Hi
> > 
> > I'm new here. I see most of the projects are done in Verilog. Why Verilog?
> > Most school teach VHDL.... My university teach VHDL.
> > I really don't want to juggle two languages.
> 
> You should ask your school (and the other schools you are
> referring too), most of the industry is using Verilog.
> Search the archives, I have posted a message a while back
> in which the Synopsys CEO makes a statement that VHDL is
> dead. Which is probably not quite true, but shows you that
> the industry is at least trying to steer in to one direction ...
> 
> Regards, 
> rudi               

Hello! I've been lurking on this list for several weeks now and thought I'd 
poke my head up here. I graduated from Virginia Tech. Like most schools, VT 
taught VHDL at the time but not Verilog. Now that I experiment with FPGAs I 
use Verilog; for some reason I just like it better. I don't know about other 
schools, but I do know why VT taught VHDL. A couple of the professors were on 
the VHDL specification committee. They are also the ones who taught the 
courses and wrote the book we used. There's a definite advantage to this; the 
professors were able to explain not just the how's, but also the why's of 
VHDL. I don't see it as a major problem that I prefer a language I learned on 
my own; the concepts are similar enough that it was worth taking the VHDL 
course when I was in school.

Todd Fleming
flemingcnc.com

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