Re: [oc] opencores status

["Ling Su" <lingsu@palmmicro.com>]

Dear Lampret,

This is S.J. Lee.  I am studying your OR1001 VHDL code.  I found that in
your document of native bus of or1001, irqn[1-0] are input ports.  But in
your VHDL code, you declare IRQN[1-0] as output ports from OR1001 CPU.  Is
there any special reason to do that?  It has also indicated that you have a
FPGA board for OR1K.  Is this FPGA synthesized by using your OR1K VHDL code?
In your VHDL code, does OR1K accept any IO interrupt?  What is the status of
your OR1K FPGA, is it functional?

Looking forward to hearing your reply.

Best Regards,
S.J.