Re: [oc] Questions about OR1k SDRAM

["Damjan Lampret" <lampret@opencores.org>]

> I'd like to contribute

Great. Perhaps you can subscrib e to openrisc mailing list.

> as much as I can. When browsing through the available materials on the
> core, I ran into the following question about the SDRAM:
>
> What kind of SDRAM controller does the OR1k core use? Does it support
> burst mode (read/write)? The SDRAM controller posted in the SDRAM project
> does not mention the usage of burst mode. The draft OR1K Native Bus
> Interface document mentions a Burst control line.
> http://www.opencores.org/cores/or1k/OpenRISC1000_Native_Bus_Interface.pdf
> However, the opencores SDRAM controller project doesn't currently handle
> burst mode.  Does this mean the OR1K project has written their own SDRAM
> controller?

I have two implementations of OR1K. OR1001 w/o caches and burst support
(optimized for size) and another OR1003 with caches and burst support (and
with bug in data cache controller that handles bursts related to the data
cache). OR1003 can break bursts to single transactions and use Joon's SDRAM
controller. Joon will add burst support when we'll need it real badly.

regards, Damjan