[oc] Questions about OR1k SDRAM

[CHEN ZHANG <chenzh@cory.eecs.berkeley.edu>]

I'm a fourth year college student at UC Berkeley, majoring in EECS. I need
to incorporate a CPU core on an FPGA project. I have experience with FPGA
tools/hardware and computer architecture, in particular, Xilinx FPGA chips
and MIPS architecture. I can dedicate project time to the design of the
CPU. Since OR1k seems to me a very promising core, I'd like to contribute
as much as I can. When browsing through the available materials on the
core, I ran into the following question about the SDRAM:

What kind of SDRAM controller does the OR1k core use? Does it support
burst mode (read/write)? The SDRAM controller posted in the SDRAM project
does not mention the usage of burst mode. The draft OR1K Native Bus
Interface document mentions a Burst control line.
http://www.opencores.org/cores/or1k/OpenRISC1000_Native_Bus_Interface.pdf
However, the opencores SDRAM controller project doesn't currently handle
burst mode.  Does this mean the OR1K project has written their own SDRAM
controller?


From: Chen Zhang
Email: chenzh@cory.eecs.berkeley.edu