[pci] PCI update

["Miha Dolenc" <mihad@opencores.org>]

Hello everyone!

    I have added WISHBONE slave interface and some acompaniing modules to
CVS. Test bench also includes configuration space and decoder
instantiations. RTL seems to work fine, I will try and synthesize module by
module tomorrow and see how it goes. At this time PCI master interface ( the
other side of a bridge ) is just simulated, since we don't have it yet ;-( .
All modules are available here, if anyone is interested:

http://www.opencores.org/cvsweb.shtml/pci/

New modules are delayed_sync and wb_slave. I've also made some changes to
fifo_control.v in FIFOs module.

Have a nice day!

Regards,
    Miha Dolenc


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