[pci] PCI TB

[Oliver Amft <oam@oamx.net>]

Hi Ovidiu, hi all,

I have actually found some time and browsed through the PCI TB VHDL
sources. 
What did you find particular bad about the master tb? This
pseudo-processor aproach is certainly not the all solving thing but
enough for quick testing...tell me what do you think!

Maybe one day we should have a fully featured processor based PCI
testbench - but this would start a project on its own ;-) (Anyone
interested in such a TB??)

Cheers
Oliver



> 2001-06-08 11:32
> To:	pci@opencores.org, olupas@opencores.org
> cc:	 
> Subject:	[pci] Re: PCI Verification
> 
> Ovidiu, thanks for the simulation files. I will walk through them and
> try to develop some ideas regarding the testing. Maybe we can discuss
> the testbench design afterwards. IMO it would be a good idea if we can
> commit the project to one HDL (but I am not sure about this). Miha and
> Tadej are using Verilog. I am quite new to Verilog. Are you using the
> NCSim too (for Verilog designs)? The Alliance Suite supports only VHDL,
> right?
> Progress is very low at the moment, I am trying to set up some stuff
> too.
> Cheers,
> Oliver

> 2001-06-07 08:47
> To:	"Oliver Amft" <oam@oamx.net>, <pci@opencores.org>, <mihad@opencores.org>
> cc:	 
> Subject:	Re: PCI Verification
> Oliver, I am not porting to Verilog the PCIsim, or, at least, not rigth now.
> If you want to, I will be glad to help you as much as I can. But, IMO, the
> PCI master
> should be done in a total different way - the current version is an
> improvement of one
> of my friends and I do not like it. ;) The Target is mine, and I do like it
> !!! ;)))
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