[pci] pci bridge

["Mike Johnson" <mikej@freeuk.com>]

Tadej,

Thanks for the quick response.
Could you send me what you have so far for the WB modules so I can build a
simulation model and get an idea of your naming convention.
 It would be nice if the Initiator & Target modules have both single cycle
and burst support, but to make the thing work at 66Mhz or above the back end
interface design is critical.
How many BAR's were you thinking of supporting ?

I'll put together a top level Target module over the next day or so, and
translate to Vhdl your WB bits.

Maybe we do both Verilog & Vhdl versions !

Cheers,
Mike

p.s. I think the spartan II and virtex I's may use the same die.

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