Re: [pci] pci bridge

["Tadej" <tadej@opencores.org>]

Hi Mike !

First the progress of finished and tested modules:
- FIFO (for PCI Target to WB Master & WB Slave to PCI Master)
- Configuration space (PCI Header type 00h + Device specific registers)
- Address decoder with Image Translation (for each image maping)

Finished modules but almoest tested (1 to 3 days left):
- Wishbone Slave (missing coments in test bench and some other files)
- Wishbone Master

As you can see, we need a PCI Master (Initiator) and a PCI Target
modules. If you can help in any way, it would be nice and we all can
gain very soon FREE PCI to WB bridge.


We write in Verilog, but we have a Verilog/VHDL tools, so VHDL code
is also fine (later it can be translated to Verilog). We also have
Spartan-II
(Virtex similar but smaller) PCI Development board.


Hope to hear from you soon.

Best regards,
                    Tadej


----- Original Message -----
From: "Mr mike johnson" <mikej@freeuk.com>
To: <pci@opencores.org>
Sent: Friday, July 13, 2001 10:32 AM
Subject: [pci] pci bridge


> Hi guys,
>
> I may be able to help you with the PCI core. I have a lot of experience
> with Xilinx Virtex devices and have worked on PCI initiator / target
> code before. Additionally, I have a vhdl tool set and access to real
> hardware.
>
> A simple wishbone to PCI bridge would seem to be the way forward for
> SOC designs.
>
> Could you send me any work in progress ?
>
> Cheers,
>
> Mike.
>
>
>
> --
> --
> To unsubscribe from pci mailing list please visit
http://www.opencores.org/mailinglists.shtml
>

--
To unsubscribe from pci mailing list please visit http://www.opencores.org/mailinglists.shtml