Re: [oc] modulo arithmatic hardware

[Ionita Mihai <ionita@brasov.isratech.ro>]

Hi guys,

I'm new on this mail list, and I see the mail traffic regarding modulo
design.

I had the same problem when I made an RSA module. When I implement the
modulo operation I put toghether the mult operation and divider.
I used shift right algorithm for mult. operation and at every step I made
an substraction operation (modulo).

Regards,
Mita.

For more details I will send a schematic for who is interested.



On Thu, 7 Mar 2002, Ali Mashtizadeh wrote:

> I have a similar problem. I was going to use a cascade divider/modulo
> function but I want it to take no more than 2 or 3 clock cycles. Yet I
> need it to be really fast and the cascade divider/modulo function isn't
> fast enough. Any suggestions. Or any implementations. Maybe I mest up my
> version. Verilog or VHDL will do if you give example codes.
>
> Ali
>
> jae lim wrote:
> >
> > Hello everyone
> >
> > Does anybody know how to design a modulo N(N>=16)
> > logic that using as less clock cycle as possible?
> >
> > Thank you in advance.
> >
> > Jay
> >
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