Re: [oc] modulo arithmatic hardware

[Jean Masson <Jean.Masson@lium.univ-lemans.fr>]

Search on the Swiss Federal Technical Institute of Zurich (ETHZ) site. Dr Zimmermann gives a
combinatorial
divider (inverse of combinatorial multiplier).

Ali Mashtizadeh a écrit :

> I have a similar problem. I was going to use a cascade divider/modulo
> function but I want it to take no more than 2 or 3 clock cycles. Yet I
> need it to be really fast and the cascade divider/modulo function isn't
> fast enough. Any suggestions. Or any implementations. Maybe I mest up my
> version. Verilog or VHDL will do if you give example codes.
>
> Ali
>
> jae lim wrote:
> >
> > Hello everyone
> >
> > Does anybody know how to design a modulo N(N>=16)
> > logic that using as less clock cycle as possible?
> >
> > Thank you in advance.
> >
> > Jay
> >
> > __________________________________________________
> > Do You Yahoo!?
> > Try FREE Yahoo! Mail - the world's greatest free email!
> > http://mail.yahoo.com/
> >
> > --
> > To unsubscribe from cores mailing list please visit http://www.opencores.org/mailinglists.shtml
>
> --
> To unsubscribe from cores mailing list please visit http://www.opencores.org/mailinglists.shtml


--
To unsubscribe from cores mailing list please visit http://www.opencores.org/mailinglists.shtml