[oc] OpenRISC with "known" architectures.

["ULF SAMUELSSON" <ulf.samuelsson@mbox308.swipnet.se>]

I saw that you guys were threatened by ARM Ltd, if you tried to do an ARM architecture.
FYI, at least some of their patents are on a very loose ground in my opinion.
Prior art, or simply not appliable.
For instance , their "patent" on the THUMB architecture relies on
a hardwired instruction set, which is by definition not applicable 
on an FPGA implementation ,since you can always reload the FPGA with something else.
Another way to go around the patent is to let the ARM mode execute 33 bit instructions
and the thumb mode to execute 32 but instructions.
Third way is to have 2 extra bits on the databus for instruction fetch
which for every instruction determines if it is ARM or THUMB together with the

Extra Bit 0 = 0: use PSR.T to determine ARM or THUMB
Extra Bit 0 = 1: Use Extra bit 1 to determine ARM or THUMB decoding.
    The extra bits convert the multiple instruction set to become a single instruction set
    Extra bit 0 can of course be hardwired (outside the core) to make the core
This can also be used with a decompressing instruction cache.
If you decompress the Thumb instructions into the cache, the core only needs to
execute the ARM instructions, making the part a single instruction set computer
actually invalidating most of their patents.
Decompressing Instruction caches were described alreay by a Professor Pattersson in 1983.

The National Semiconductor HPC architecture in itself probably invalidates the patent
since You can argue it already it implements the idea described in the patent.

Would be fun to see a free ARM implementation.

Best Regards,
Ulf Samuelsson    
ulfs@dof.se