[oc] Memory Controller Help

[Soban Shoeb Chawre <sobanc@nital.stpp.soft.net>]

file:///tmp/nscomm40-sobanc/705/tmp0/edt1.html




 
Hello All,

I was trying to test the Memory controller with only SRAM.
But tetst bench gives following error.

Is any kind of changing of parameters is required?
Plz let me know.

Thanks,
Soban.

*****************************************************
* WISHBONE Memory Controller Simulation started ... *
*****************************************************
 

MC_TIMING SM: Entered non existing state ... ( 0.0 ns)

INFO: WISHBONE MASTER MODEL INSTANTIATED (test.m0)
 

"./mt58l1my18d.v", 202: Timing violation in test.sram0b
$width( negedge Clk:1.0 ns, : 1.0 ns, limit: 2.3 ns );

"./mt58l1my18d.v", 202: Timing violation in test.sram0a
$width( negedge Clk:1.0 ns, : 1.0 ns, limit: 2.3 ns );
 

"./mt58l1my18d.v", 204: Timing violation in test.sram0b
$period( negedge Clk:1.0 ns, : 5.0 ns, limit: 6.0 ns );

"./mt58l1my18d.v", 204: Timing violation in test.sram0a
$period( negedge Clk:1.0 ns, : 5.0 ns, limit: 6.0 ns );

......................................................
: :
: Short Regression Run ... :
:....................................................:
 
 

*****************************************************
*** SRAM Size & Delay Read Test 1 ... ***
*****************************************************

Size: 1, Delay: 0
 

*************************************

ERROR: Watch Dog Counter Expired

*************************************
 
 

$finish at simulation time 30170.0 ns
V C S S i m u l a t i o n R e p o r t
Time: 30170000 ps
CPU Time: 1.110 seconds; Data structure size: 16.2Mb
Thu Aug 14 13:12:21 2003