Re: [usb] Please help with a USB DPLL

[mdennis97@hotmail.com]

hi, Mr. rudi:

I am not so clear about the following code in usb_rx_phy.Maybe there 
are some special functions that I didn't grasp:

// Compensate for sync registers at the input - allign full speed
// clock enable to be in the middle between two bit changes ...
always @(posedge clk)
	fs_ce_r1 <= #1 fs_ce_d;

always @(posedge clk)
	fs_ce_r2 <= #1 fs_ce_r1;

always @(posedge clk)
	fs_ce_r3 <= #1 fs_ce_r2;

always @(posedge clk)
	fs_ce <= #1 fs_ce_r3;

Can I replace them with "assign fs_ce = fs_ce_d;"? If not, why?


Regards

Dennis
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