Re: [pci] Bus command

[Madhusudhan Rao <madhu_sudhana_rao@yahoo.com>]

hai,
    I am sending answers for ur questions. I hope
these are sufficient to u. Let me know whether these
are useful to u or not.
  Cacheline size is in units of 32-bit words when it
supports burst mode.It has to support Memory Read Line
or/and Memory Read Multiple command.

   Prefetch means you are fetching the data from
memory or from I/O device before u use. This will be
useful when u are using burst dataphase mode to avoid
delay of fetching data when ever u need.

    The transaction completes at the source before it
actually completes at the intended destination. How it
happens is the transaction is captured by an
intermediate agent for example a bridge from one bus
to another. This allows the source to proceed with the
next operation while the transaction is still making
its way through the system to its ultimate
destination.

regards
Madhu
mrao@avanticorp.com
madhu_sudhana_rao@yahoo.com


--- wilton@mail.usa.com wrote:
> Dear All,
> 
> I am a novice in RTL design and trying to understand
> the PCI bridge 
> core. Could anyone here help me to understand the
> meaning of pre-
> fetch, catchline, post write...? Under what
> circumstance shall they be 
> implemented? I appreciate very much could anyone
> provide me any 
> necessary information on it. 
> Let's say if I'd like to implement an Ethernet MAC
> controller with PCI 
> interface, shall I implement these stuff? 
> BTW, Would anyone know where to get the MAC
> controller with PCI 
> interface?
> 
> Awaiting your reply
> with regards
> 
> Wilton
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=====
MadhusudhanaRao.M

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