Re: [pci] RE: [pci] Problems compiling PCI core and test bench for Modelsim

[jamarek@rockwellcollins.com]

All:

I think that some of the problems I am seeing are due to the fact that the
simulator and synthesizer that ws used looks in the files in the dir and
grabs things.  I notices that the pci_constants.v is not included in top.v.
For me that means the bufif are never instantiated.  Knowing that, I am
going to go through all of the files to determine what the dependencies are
and assure that the proper includes are present.

Jim




sky@virgilio.it@opencores.org on 03/07/2002 03:48:17 AM

Please respond to pci@opencores.org

Sent by:    owner-pci@opencores.org


To:    pci@opencores.org
cc:

Subject:    [pci] RE: [pci] Problems compiling PCI core and test bench for
       Modelsim


I've encountered some problems like yours. Now I try to modify sintax of
some blocks to compile files with "vcom".
I hope to be able to do this because pci core is a chip way to obtain a
good pci interface with a standard local intarface.
If I obtain some good results I'll tell you.
good work
Massimo

-- Messaggio originale --

>All:
>
>I am trying to compile this project with Modelsim and I get the following
>errors.  I downloaded the entire project and used the attached script to
>compile.  The compile.log file is my errors.  I can fix the errors, but
this
>is making me wonder if I am missing something or have out of date files.
> I have never used verilog before, but the free PCI core is very appealing
>so I thought I would evaluate it.  Any help would be much appreciated.
>
>Thanks,
>
>Jim





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