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Re: [pci] PCI target
Miha Dolenc wrote:
> Hi again,
>
> now, I would call that cheating ;-) . But there are still some issues
> that remain - this PCILOGIC block seems to control only clock enable signal
> depending on the state of IRDY and TRDY signals. But there are other signals
> that don't have any relationship to IRDY and TRDY handshaking - for example
> address phase ( no IRDY nor TRDY are asserted then ) and PAR and incoming
> byte enables for target reads and so on. I'm having problems here too,
> because let's say some external master is doing a read through a target
> interface. I have to calculate PAR from incoming CBE signals (7ns
> constraint) and outgoing data that target is driving. Here PCI logic block
> doesn't help if I'm not mistaking?
>
Yep, you are absolutely right. I think the address timing is only a
problem if you are trying to do "Fast" decode. I would go for the
"Medium" decode in FPGAs. The PAR timing then appears to me to be the
main signal where you really have to push things.
I was partly through a PCI design 7 or 8 months ago (I've been buried in
work since then). But the way I figured the PAR timing could be made was
to not use the output FF in the IOB for the PAR signal, or the input FFs
for the CBE signals.
Instead, I had the CBE signals come in directly to a LUT, along with a
single bit for the rest of the signals on which parity had already been
calculated. Fortunately, there is an extra XOR gate in the Virtex slice,
so a 5 input XOR is easy. I latched that with the FF in the same slice,
and then output that to the PAR pin. I think I even made a small test
circuit and ran place and route and timing, to verify that this would
meet the timing specs.
Mike wrote:
> You are absolutely right, the Xilinx PCI core cheats using exactly those
> 'hidden' resources.
> Not sure how we can compete against that.
>
There is nothing wrong with using them yourself. All the Xilinx tools
understand the PCILOGIC primitive just fine, so go ahead and use it.
Duane
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