Re: [pci] PCI target

["Miha Dolenc" <mihad@opencores.org>]

Hi all,
it's been a while since we last talked here!

In fact, I did PCI master already and I'm resolving problems regarding
timing for three weeks now. It's the problem that Duane is talking about - I
want it generic and therefore problematic ;-( . I don't know anything about
PCILOGIC yet - I will try and find it on the internet. Duane - do you know
if this PCILOGIC block can be force used by specifying some constraints. If
so - is this user, synthesys or physical constraint?
Some syntax example would be nice also ;-) .

Thanx for your interest!

Regards,
    Miha

----- Original Message -----
From: "Duane Clark" <dclark@akamail.com>
To: <pci@opencores.org>
Sent: Saturday, September 01, 2001 2:13 AM
Subject: Re: [pci] PCI target


> MikeJ wrote:
>
> > Tadej & people,
> >
> > Still alive !
> >
> >
> >
> > Sorry things have been quiet this month - I've been away longer than
> > expected and have just got home.
> >
> > I have built a (prototype & simple - dummy backend i/f) virtex 300e-5
> > pci target which meets my draft 33mhz timespecs.
> >
> > However for faster speeds I strongly suspect I am going to have to use
> > virtex specific cells which would have to be rloc'd.
> >
> > What are the general feelings about introducing vendor specific versions
?
>
>
> I just want to make sure that you are aware of the "PCILOGIC" special
> block that is on the virtex/spartan II devices. It is designed for the
> IRDY/TRDY signal handshaking, to allow you to meet the stringent timing
> requirements, especially when you get to doing a bus master.
>
> I personally think that making a completely generic VHDL design for
> FPGAs is going to be extremely difficult.
>
> Duane
>
>
>
>
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