RE: [fpu] multiplier

[Jamil Khatib <jamilkhatib75@yahoo.com>]

Hi,

I made an overview of your cores it seems to me it is
not fully IEEE-754 compliant "even violates some
rules" they are more like generic floating point
cores.

You have also to know that this project should be full
system where all cores shoul communicate on correct
way and software should give much support for them.
For example the status flags should be controlled by
Software. where the HW generates the exceptions and
teh software stores teh SW flags and does not depend
on HW ones. "this is a recommendation by IEEE-std
because else lot of exceptions will alwys interrupt
the system".

Please check my overview of the system block diagram
how it looks like at BlockDiagram.eps under the FPU
direcotry.

I'll give more explaination about that diagram

Note: why do you want get everything fast do we have a
dead line or somthing?


Regards
Jamil Khatib


--- Rudolf Usselmann <rudi@inet.co.th> wrote:
> 
> 
> > From: owner-fpu@opencores.org
> [mailto:owner-fpu@opencores.org]On Behalf
> > Of Jamil Khatib
> > Subject: RE: [fpu] multiplier
> > 
> > 
> ....
> > I saw that you used the * operator but as I
> remmber
> > doen not give good performance for this operator
> "It
> > has been long time since I used sysnopsys". I
> think in
> > order to get good performance you have to use a
> > multiplier from DesignWare.
> > If you see that it gives good performance thats
> OK.
> 
> Synopsys FPGA Compiler does choose an multiplier
> from
> it's DesignWare library.
> 
> > > If you think you
> > > can write a multiplier that will be faster then
> what
> > > Design Compiler will
> > > generate, then go for it !!!  (I wouldn't hold
> my
> > > breath thou ... ;*)
> > 
> > I'll try to do that.
> 
> OK, good luck !
> 
> > Anyhow if I am going to write it, it will be in
> VHDL
> > if you like we can discuss the design together and
> you
> > write teh verilog code and me the vhdl.
> > 
> > Anyhow we need to define the spec of the
> interfaces
> 
> I think it will be better if I write it in Verilog,
> and you
> can translate it to VHDL. You'll be busy with the
> multiplier
> anyway, and I want to get the entire design done
> ASAP, so I
> can spend some time integrating and optimizing it.
> 
> > Regards
> > Jamil Khatib
> 
> rudi


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