RE: [fpu] multiplier

["Rudolf Usselmann" <rudi@inet.co.th>]

> From: owner-fpu@opencores.org [mailto:owner-fpu@opencores.org]On Behalf
> Of Jamil Khatib
> Subject: RE: [fpu] multiplier
> 
> 
...
> I saw that you used the * operator but as I remmber
> doen not give good performance for this operator "It
> has been long time since I used sysnopsys". I think in
> order to get good performance you have to use a
> multiplier from DesignWare.
> If you see that it gives good performance thats OK.

Synopsys FPGA Compiler does choose an multiplier from
it's DesignWare library.

> > If you think you
> > can write a multiplier that will be faster then what
> > Design Compiler will
> > generate, then go for it !!!  (I wouldn't hold my
> > breath thou ... ;*)
> 
> I'll try to do that.

OK, good luck !

> Anyhow if I am going to write it, it will be in VHDL
> if you like we can discuss the design together and you
> write teh verilog code and me the vhdl.
> 
> Anyhow we need to define the spec of the interfaces

I think it will be better if I write it in Verilog, and you
can translate it to VHDL. You'll be busy with the multiplier
anyway, and I want to get the entire design done ASAP, so I
can spend some time integrating and optimizing it.

> Regards
> Jamil Khatib

rudi