RE: [openrisc] sram_top.v

["Michael Scott" <mike.scott@jennic.com>]

Hi Jerry
        I've recently synthesised the OR into XC2V4000 using synplify_pro
(7.2.3)
The code went through first time. However I also experienced difficulties
when using
vendors proprietary synthesis engines;  namely XST in the case of Xilinx.
Unfortunately "real" synthesis tools don't come cheap & I appreciate that if
quartus is the
only synth engine you have access to then maybe the code does need to be
locally modified to
pass through (not an ideal solution)
It would be nice if the code passed through all synth tools;  Synplify,
Precision, quartus, xilinx etc
but as each tool has it's own idiosyncrasies this is unlikely.

Regards,

Mike

-----Original Message-----
From: owner-openrisc@opencores.org
[mailto:owner-openrisc@opencores.org]On Behalf Of Jerry English
Sent: 15 May 2003 16:35
To: openrisc@opencores.org
Subject: [openrisc] sram_top.v


Greetings,

I am trying to compile the SOC for Altera's Stratix. I have made many many
memory
models. Now I am looking at the file mem_if/sram_top.v.

At first the sram_top.v caused an internal error in quartus. I commented out
the `define SRAM_GENERIC in the sram_top.v file.

Now Quartus is complaining about an undefined variable wb_err. 
I copied assign wb_err = wb_cyc_i & wb_stb_i & (delay == 2'd0) &
(|wb_adr_i[23:21]);  to the `else module but
got another error message about delay not being defined. 

So at this point I'm pretty uncomfortable about copying, commenting and
pasting into code that I 
know next to nothing about.  

I would have thought that just commenting out the `define SRAM_GENERIC would
have done the trick.
Where did I go wrong?

regards
Jerry



--
To unsubscribe from openrisc mailing list please visit
http://www.opencores.org/mailinglists.shtml

winmail.dat