[openrisc] Control Systems' IP Cores.

[Manuk Shemsyan <s_manuk@freenet.am>]

Hello lampret,

Monday, January 6, 2003, 2:09:32 PM, you wrote:

loo> Heya !

loo> Yes this is a typo. IOt will be corrected in the new revision of the 
loo> manual.

loo> regards,
loo> Damjan


loo> ----- Original Message ----- 
loo> From: Marko Mlinar <markom@o... > 
loo> To: openrisc@o... ,  Mar燰 Bolado 
loo> <mbolado@t... > 
loo> Date: Wed, 18 Dec 2002 14:07:16 +0100 
loo> Subject: Re: [openrisc] Field CWS in ICCFGR 

>> 
>> 
>> On Wednesday 18 December 2002 11:29, Mar燰 Bolado wrote: 
>> > Hello: 
>> > Why do the Instruction Cache Configuration Register have a 
>> field containing 
>> > the "Cache Write Stategy"? Does that mean that writing in IC 
>> is allowed? If 
>> > so, why don't you implement a Cache Block Flush Register for 
>> instruction 
>> > cache? I guess that CWS in ICCFGR is a typo in document, but I 
>> would like 
>> > to confirm it. Thank you in advance. 
>> > Mar燰 Bolado 
>> 
>> Cache write strategy is optional to implement and means e.g. LRU, 
>> FIFO,... 
Hi everybody,
I am looking for IP Cores suitable for Industrial Control Systems
design or anything like these.
1. Quad Encoders (for closed servo motor control),
2. MUX Ports
3. PWM Controllers and DSP gates dedicated for 3-phase AC motor vector
   control technique...

Happy New Year!
Best regards,
 Manuk                            mailto:s_manuk@freenet.am

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