回信： [openrisc] insn decoder and COFF loader

[jimmy87@sunplus.com.tw]

Hi Damjan,
I think the insn in (h.bf, h.bnf) branch delay slot could be 2-byte or 4-byte
wide.
But if we want to design for simplicity or it's unnecessary
to have the two choices(either performance or compiler),
I think we can let it be 2-byte or 4-byte.
But we still have to make sure that only one insn could exist in the delay slot.
As to unconditional jump, we can make it fixed if you want.
What do you think?
As to my point of view,
I prefer only one insn in delay slot and the insn is only 2-byte wide in
OR16 ISA.
Best regards, Jimmy