[openrisc] Re: INT and CS on OR1K was: [oc] documentation problem

["Damjan Lampret" <lampret@opencores.org>]

> IMHO ~CSn signals and ~IRQn should be out of the processor
> core, they are independant.

And they are. This spec is about native bus and native BIU. Processor core
has only one ~IRQ. And processor core doesn't have anything with ~CS. Chips
selects are handled by BIU. Native BIU is not part of central processor
core.

> Either provide 1 interrupt or 1 fast interrupt and one normal interrupt
> as in the StrongArm. Interrupt controller can be very system
> dependant.

I agree. You can see native BIU as a component of final OR1K compliant
processor. You have BIU and you have processor core.

> Another solution used by ColdFire is to provide a special bus
> acces where the core sample the interrupt vector  on the data bus
> LSByte.
>

I don't like this.

> I did'nt understand the aim of ~BURST ...
>

Well at the moment it functions as a status signal. Things around burst
signals will definately change in the future.

regards, Damjan