[openrisc] Fw: 回信： or32

["Damjan Lampret" <lampret@opencores.org>]

----- Original Message -----
From: Damjan Lampret <lampret@opencores.org>
To: <jimmy87@sunplus.com.tw>
Cc: Johan Rydberg <johan.rydberg@netinsight.se>
Sent: Monday, March 20, 2000 6:39 PM
Subject: Re: 回信： or32


> >
> > in or1-ab.h,
> > it seems that div insn is lost.
> >
>
> Actually there was no div insn. Divisions are usually rare and also take a
> lot of die space for a fast divide unit. Anyway I am lately thinking about
> booth's multiplier which can also be used for divison. In order words I am
> thinking we could use div insn.
>
> > The other questions:
> > 1. why bal and jal? it seems these two are the same.
>
> I am not sure if we need both. Difference is that bal is relative and jal
is
> abolute. Do we need this?
>
> > 2. it seems that no multiply-and-subtract insn.
>
> Correct. Do we need mas?
>
> > 3.you don't wanna use "multiply unsigned" multiplication?
> >    it seems that only the opcode doesn't specify it's a signed or
unsigned
> >    multiplication.
>
> Here you are right. I was careless when preparing the list.
>
> > 4.you discard the data cache operation insn?
>
> Yes. I think all implementation hardware related functions should be done
> via special regs and we should have any special insns to do that. If so
our
> ISA is more clean and hardware independent. Anyway we must define cache
> operations in architecture and I am doing this right now.
>
> > 5.the sched insn?
>
> Well do you think we need sched insn? Static (compiler) scheduling has
> benefits and drawbacks. Since I think our processors will be more scalar
> then superscalar sched doesn't make much sense. Interested parties will
buy
> Intel's and Motorola's processors when they will want power of
superscalar.
> Anyway we can always make architecture number II later when we'll making
> superscalar processors. ;-)
>
> regards, Damjan
>
>