Re: [fpu] Architecture

["Damjan Lampret" <damjan.lampret@arnes.si>]

> >
> > I think x86 type of FPU is not what we want to do. Our is not like
> > "coprocessor" but it is a functional (sometimes a.k.a execution) unit. I
> > think you both agreed on this and I like it too. So we should make FPU
that
> > fits in parallel with load/store unit, integer unit etc. All insn
> > decode/issueing is done by the common insn decoder/issue stage. So our
CPU
> > has LSU, IU, FPU (and perhaps some other units). At least FPU is
optional.
>
> Could you tell us about the OR1K execution units interface
>

Well execution units gets both operands (either from register file,
sign-extended immediate or what ever - it is responsibility of the issue
stage to deliver propoer operands to particular execution unit) and
operation code (which operation must be carried out on operands). Pipeline
stalling and other control operation over pipeline are carried out in
datapath controller and are not part of execution units (so datapath
controller takes care for multicycle FP instructions).

> >
> > The first question that pops up is do we use pairs of 32 bit registers
to do
> > double precision
>
> may be we can make it dependent on the instruction if its operand is
single
> precision then use 32 bit reg if it is double use two regs. Also you need
> special consideration in the load store unit.

Perhaps.

>
> > (I am not talking about internal represention that can be
> > 80 or even more bits)?
>
> The 32-64-80or 128 bits represent different precessions check teh attached
file.
>

I know that. I have problems since OR1K architecture is going to be 32/64
bit architecture (with special OR16 instruction set which insns are 16 bits
wide and operating on 32-bit data). My problem is double and better
precision in implementation that is only 32-bit (implementation is actual
processor implementing particular architecture). So if you want to have
double precision FP in implementation that is only 32-bit integer you have
problem fetching data from register file since register file has 2 read
ports (if we are talking ordinary scalar implementation). How do you get 2x
64-bit from register file in the same cycle?

> > In this case would would need 4 read ports on
> > register file.
>
> Can you explain more why do we need such register file

See above.

regards, Damjan