Re: [fpu] Architecture

[Jamil Khatib <jamilkhatib75@yahoo.com>]

Damjan Lampret wrote:

> I was away for the last six days so I'll go in discussion with you from now
> on.
>

Welcome Damjan,
It took me some time to reply because I want to make sure about IEEE
representation. I attached summary of IEEE format

>
> I think x86 type of FPU is not what we want to do. Our is not like
> "coprocessor" but it is a functional (sometimes a.k.a execution) unit. I
> think you both agreed on this and I like it too. So we should make FPU that
> fits in parallel with load/store unit, integer unit etc. All insn
> decode/issueing is done by the common insn decoder/issue stage. So our CPU
> has LSU, IU, FPU (and perhaps some other units). At least FPU is optional.

Could you tell us about the OR1K execution units interface

>
> The first question that pops up is do we use pairs of 32 bit registers to do
> double precision

may be we can make it dependent on the instruction if its operand is single
precision then use 32 bit reg if it is double use two regs. Also you need
special consideration in the load store unit.

> (I am not talking about internal represention that can be
> 80 or even more bits)?

The 32-64-80or 128 bits represent different precessions check teh attached file.

> In this case would would need 4 read ports on
> register file.

Can you explain more why do we need such register file

> Perhaps FPU should be scalable so that you can either do both
> single and double or just single precision since at least implementations
> that are die area sensitive won't use double precision.
>

Sure

>
> regards, Damjan
>
> PS I like PPC architecture manual and description of FP operands and MPC7xx
> manual and description of FPU (it doesn't go into microarchitecture details
> of course).
>

Do you have the manual?

>
> ----- Original Message -----
> From: Jamil Khatib <jamilkhatib75@yahoo.com>
> To: <fpu@opencores.org>
> Sent: Sunday, April 23, 2000 8:23 AM
> Subject: Re: [fpu] Architecture
>
> [cut]
> > After reading the 387SX coprocessor and IA64 manual, I have some questions
> and
> > comments:
> >
> [cut]

Jamil Khatib
		Single  Double   Double-Extended  Quad-Precision
Exponent(max)	+127	+1023	+16383		  +16383
Exponent(min)	-126	-1022	-16382		  -16382
Exponent Bias	+127	+1023	+16383		  +16383
Precision(#bits)24	53	64		  113
Total Bits	32	64	80		  128
Sign bits	1	1	1		  1
Exp Bits	8	11	15		  15
Fraction	23	52	64		  112