RE: [ethmac] Reseting ethernet MAC

["Illan Glasner" <iglasner@zumanetworks.com>]

30-Jan-01

   Igor Hi,

            The main reason to have a "software reset" in addition to global reset is in case you need to reset some part of the chip while retain other part as they was before BUT this need to be done carefully, or to simple reset the whole chip.

the first case need to be considerd as for exmaple if module a and b have two state machine that handshakle between themself and you reset only module a or module b than you can get into condition you never anticipate and crashed.

on the otherhand if you have a module that reset a huge cam than you might want to be able to reset your FPGA without reseting this module as it will delete all cam entry and youwill have to re-learn all the entries once again.

taking both above considuration I would think that a global reset should be the right one for MAC design and in order to allow power up as well as software global reset you can simple have the mapped FF routed to an output pin and on the board or/and this pin and the power up reset line to the global reset of the FPGA. in order to prevent strange penomena better use a reset chip to reset your fpga and to his input hock those two line.

BTW one technique used many time in Asic is to have a software reset per clock domain which also have some risk. the best way in my opinion is to be able to close the port so there will be no incoming packet (from all side) than have a reset which can be done either by different clock domain or singal one which is syncronize to each clock domain. and so the sequance is : close the ports, reset the Asic, open the port, this way the whole chip start to work togther and there is no risk of some module start to work before other.

have a nice day

   Illan



-----Original Message-----
From: Igor Mohor [mailto:igorm@opencores.org]
Sent: Wednesday, January 30, 2002 6:36 AM
To: Ethmac@Opencores. Org
Subject: [ethmac] Reseting ethernet MAC


Hi, Guys,

I'm thinking how to best reset ethernet core. At this point host interface
is asynchronously reset by the WISHBONE reset (wb_rst_i). All other cores
are asynchronously reset by a reset signal that is an output from registers
(r_Rst). So there are two async. reset signals and that  causes problems in
routing.

My question is how to reset all this cores?
Some flipflops are clocked my MTxClk, some by MRxClk. Reset from register
(r_Rst) is set by WISHBONE clock (wb_clk_i).

I would say that the current solution is not ok.
There are many different options:

1.) Everything remains as it is except that r_Rst is synchronized to MTxClk.
New signal (r_Rst_tx) async. resets MTxClk clocked flipflops. r_Rst is also
synchronized to MRxClk. New signal (r_Rst_rx)  async. resets all MRxClk
clocked flipflops. Routing problems remain (actually increase because there
are 3 async. reset signals).

2.) Same as in 1.) except that r_Rst_tx and r_Rst_rx synchronously reset
flipflops. Core size will increase probably for some 20 %.

3.) We don't need an extra reset signal from registers. Host reset signal
wb_rst_i resets all cores (but it is not synchronized to MTxClk or MRxClk).

4.) Same as 3.) but  wb_rst_i is synchronized to tx and rx clocks.

There are many other combination.

Is there some "standard" solution for that. Does anybody have experiance
with that and might propose the right solution?

Thanks for your help.

Regards,
	Igor

--
To unsubscribe from ethmac mailing list please visit http://www.opencores.org/mailinglists.shtml
--
To unsubscribe from ethmac mailing list please visit http://www.opencores.org/mailinglists.shtml