[ethmac] Reseting ethernet MAC

["Igor Mohor" <igorm@opencores.org>]

Hi, Guys,

I'm thinking how to best reset ethernet core. At this point host interface
is asynchronously reset by the WISHBONE reset (wb_rst_i). All other cores
are asynchronously reset by a reset signal that is an output from registers
(r_Rst). So there are two async. reset signals and that  causes problems in
routing.

My question is how to reset all this cores?
Some flipflops are clocked my MTxClk, some by MRxClk. Reset from register
(r_Rst) is set by WISHBONE clock (wb_clk_i).

I would say that the current solution is not ok.
There are many different options:

1.) Everything remains as it is except that r_Rst is synchronized to MTxClk.
New signal (r_Rst_tx) async. resets MTxClk clocked flipflops. r_Rst is also
synchronized to MRxClk. New signal (r_Rst_rx)  async. resets all MRxClk
clocked flipflops. Routing problems remain (actually increase because there
are 3 async. reset signals).

2.) Same as in 1.) except that r_Rst_tx and r_Rst_rx synchronously reset
flipflops. Core size will increase probably for some 20 %.

3.) We don't need an extra reset signal from registers. Host reset signal
wb_rst_i resets all cores (but it is not synchronized to MTxClk or MRxClk).

4.) Same as 3.) but  wb_rst_i is synchronized to tx and rx clocks.

There are many other combination.

Is there some "standard" solution for that. Does anybody have experiance
with that and might propose the right solution?

Thanks for your help.

Regards,
	Igor

--
To unsubscribe from ethmac mailing list please visit http://www.opencores.org/mailinglists.shtml