RE: [ethmac] Interest in Ethernet Verilog or VHDL "system model"

["Illan Glasner" <iglasner@zumanetworks.com>]

13-Mar-01

   Hi,

	Since you mention you design Asic I will jump and give you a
short warnign as not like FPGA you will have to pay quite a lot for any
extra spin even if it is only a metal one.

Personaly I belive while the MAC in the opencore did improve and change
few time it is still not in valid condition to be use to verify an Asic
MII design.

I would suggest that better you design a small behave phy as there are
not many signal and make them as random as possibale INCLUDING the clock
!!!.

or even better Contact one of the company that make MAC/PHY etc and get
a behaviroal module and hook it to your rtl code and see how it do.

Don't forget that the spen define clock in +/- ppm so you need to check
if it is +/- 100ppm for 200ppm but better do it to 800ppm just to be on
the safe side.

have a nice day

   Illan


-----Original Message-----
From: John Williams [mailto:John.Williams@TI.com]
Sent: Tuesday, March 06, 2001 3:11 PM
To: ethmac@opencores.org
Subject: [ethmac] Interest in Ethernet Verilog or VHDL "system model"



Novan or Mahmud-
I am working on an ASIC that has an
Ethernet "switch" that interfaces to
two external PHYs across two MII ports.
The internal port interfaces to an
ARM7 MCU.  We are trying to find a
good system model that we can use
to control/analyze network activity
to verify our design.  Do you guys
know of any "open" solutions that
we could use?  Could we use the
modules that are specified on the
"opencores" site by hooking them
up as external devices to our MII
ports?

Any help you can offer would be
great!

Thanx in advance for your support.

Regards-John

~~~~~~~~~~~~~~~~~~~~~~~~~~~
John W. Williams
IP Phone Design Solutions
Texas Instruments, Inc.
(303) 651-5996 -- Office
(303) 378-7626 -- Mobile
john.williams@ti.com