RE: [ethmac] fifo_synch.v

["Illan Glasner" <iglasner@zumanetworks.com>]

13-Mar-01

   Hi,

	Regardless of the actual design I do hope you are not passing
data through two stage FF to solve synconization problem as this wil
only bring you garbage results !!!.

Just think what happen if one bit of data pass the FF and the other
didn't.

IF you want to use two clock you will need a bit more line of code to do
it :-)

have a nice day

   Illan


-----Original Message-----
From: Igor Mohor (uni-mb) [mailto:igor.mohor@uni-mb.si]
Sent: Wednesday, March 07, 2001 10:09 AM
To: ethmac@opencores.org
Subject: [ethmac] fifo_synch.v


Hi, Guys.

I'm working on MII and MAC Control Module.
I see some problems in the fifo_synch.v. Data is coming from the host
and is
synchronized to the host clock. To synchronize it to the clk, you need
two
clocks and not just one (metastability).

The file should look:

always @(posedge clk)
  if (transmit_enable)
    begin
      temp_txd <= data;
      temp_tx_en <= 1'b1;
      temp_tx_er <= transmit_error;
    end
  else
    begin
      temp_txd <= 4'h0;
      temp_tx_en <= 1'b0;
      temp_tx_er <= 1'b0;
    end

always @(posedge clk)
  if (transmit_enable)
    begin
      txd <= temp_txd;
      tx_en <= temp_tx_en;
      tx_er <= temp_tx_er;
    end
  else
    begin
      txd <= 4'h0;
      tx_en <= 1'b0;
      tx_er <= 1'b0;
    end

Let me know if I am wrong.

PS.
Is somebody else working on the MII and MAC Control Module?


Regards,
	Igor