[cvs-checkins] pci/rtl/verilog wbw_wbr_fifos.v wb_tpram.v wb_ ...

[OpenCores CVS Agent <cvs@www.lampret.com>]

CVSROOT:	/home/oc/cvs
Module name:	pci
Changes by:	tadejm	02/10/17 21:49:25

Modified files:
	rtl/verilog    : wbw_wbr_fifos.v wb_tpram.v wb_slave_unit.v 
	                 top.v 

Log message:
	Changed BIST signals for RAMs.

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