[cvs-checkins] or1k/or1200/rtl/verilog or1200_dc_ram.v or1200 ...

[OpenCores CVS Agent <cvs@www.lampret.com>]

CVSROOT:	/home/oc/cvs
Module name:	or1k
Changes by:	lampret	02/10/17 19:09:05

Modified files:
	or1200/rtl/verilog: or1200_dc_ram.v or1200_dc_tag.v 
	                    or1200_dc_top.v or1200_defines.v 
	                    or1200_dmmu_tlb.v or1200_dmmu_top.v 
	                    or1200_ic_ram.v or1200_ic_tag.v 
	                    or1200_ic_top.v or1200_immu_tlb.v 
	                    or1200_immu_top.v or1200_spram_1024x32.v 
	                    or1200_spram_1024x8.v or1200_spram_2048x32.v 
	                    or1200_spram_2048x8.v or1200_spram_256x21.v 
	                    or1200_spram_512x20.v or1200_spram_64x14.v 
	                    or1200_spram_64x22.v or1200_spram_64x24.v 
	                    or1200_top.v 

Log message:
	Added BIST scan. Special VS RAMs need to be used to implement BIST.

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