[cvs-checkins] or1k/mp3/rtl/verilog/or1200 cpu.v defines.v ex ...

[OpenCores CVS Agent <cvs-checkins-agent@opencores.org>]

CVSROOT:	/home/oc/cvs
Module name:	or1k
Changes by:	lampret	01/11/13 11:02:21

Modified files:
	mp3/rtl/verilog/or1200: cpu.v defines.v except.v frz_logic.v 
	                        id.v rf.v 

Log message:
	Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc)

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