[cvs-checkins] pci/rtl/verilog bus_commands.v cbe_en_crit.v c ...

[OpenCores CVS Agent <cvs-checkins-agent@opencores.org>]

CVSROOT:	/home/oc/cvs
Module name:	pci
Changes by:	mihad	01/10/05 10:14:30

Modified files:
	rtl/verilog    : bus_commands.v cbe_en_crit.v 
	                 conf_cyc_addr_dec.v conf_space.v constants.v 
	                 cur_out_reg.v decoder.v delayed_sync.v 
	                 delayed_write_reg.v dp_async_ram.v dp_sram.v 
	                 fifo_control.v frame_crit.v frame_en_crit.v 
	                 frame_load_crit.v io_mux_en_mult.v 
	                 io_mux_load_mux.v irdy_out_crit.v 
	                 mas_ad_en_crit.v mas_ch_state_crit.v 
	                 mas_load_next_crit.v out_reg.v par_cbe_crit.v 
	                 par_crit.v pci_bridge32.v pci_decoder.v 
	                 pci_in_reg.v pci_io_mux.v pci_master32_sm.v 
	                 pci_master32_sm_if.v pci_parity_check.v 
	                 pci_target32_ad_en_crit.v pci_target32_clk_en.v 
	                 pci_target32_ctrl_en_crit.v 
	                 pci_target32_devs_crit.v 
	                 pci_target32_interface.v 
	                 pci_target32_load_crit.v pci_target32_sm.v 
	                 pci_target32_stop_crit.v 
	                 pci_target32_trdy_crit.v pci_target_unit.v 
	                 pciw_fifo_control.v pciw_pcir_fifos.v 
	                 perr_crit.v perr_en_crit.v serr_crit.v 
	                 serr_en_crit.v synchronizer_flop.v top.v 
	                 wb_addr_mux.v wb_master.v wb_slave.v 
	                 wb_slave_unit.v wbr_fifo_control.v 
	                 wbw_fifo_control.v 

Log message:
	Updated all files with inclusion of timescale file for simulation purposes.

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